? semiconductor components industries, llc, 2005 july, 2005 ? rev. 0 1 publication order number: SMBJ12AON/d SMBJ12AON 600 watt peak power zener transient voltage suppressor unidirectional* the SMBJ12AON is designed to protect voltage sensitive components from high voltage, high energy transients. this device has excellent clamping capability, high surge capability, low zener impedance and fast response time. the SMBJ12AON is ideally suited for use in computer hard disk drives, communi cation systems, automotive, numerical controls, process controls, medical equipment, business machines, power s upplies, and many other industrial/consumer applications. specification features: ? working peak reverse voltage range ? 12 v ? peak power ? 600 watts @ 1 ms at maximum clamp voltage @ peak pulse current ? esd rating of class 3 (>16 kv) per human body model ? esd rating iec 61000 ?4.2 level 4 ? low leakage < 5 a at 12 v ? ul 497b for isolated loop circuit protection ? response time is typically < 1 ns ? pb?free package is available mechanical characteristics: case: void-free, transfer-molded, thermosetting plastic finish: all external surfaces are corrosion resistant and leads are readily solderable maximum case temperature for soldering purposes: 260 c for 10 seconds leads: modified l?bend providing more contact area to bond pads polarity: cathode indicated by polarity band mounting position: any absolute maximum ratings please see the table on the following page plastic surface mount zener overvoltage transient suppressor 600 watt peak power device package shipping ? ordering information SMBJ12AONt3 smb 2500/tape & reel smb case 403a plastic cathode anode y = year ww = work week lem = specific device code yww lem marking diagram ?the ?t3? suffix refers to a 13 inch reel. http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. SMBJ12AONt3g smb (pb?free) 2500/tape & reel
SMBJ12AON http://onsemi.com 2 absolute maximum ratings rating symbol value unit peak power dissipation (note 1) @ t l = 25 c, pulse width = 1 ms p pk 600 w dc power dissipation @ t l = 75 c measured zero lead length (note 2) derate above 75 c thermal resistance from junction to lead p d r jl 3.0 40 25 w mw/ c c/w dc power dissipation (note 3) @ t a = 25 c derate above 25 c thermal resistance from junction to ambient p d r ja 0.55 4.4 226 w mw/ c c/w operating and storage temperature range t j , t stg ?65 to +150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. 10 x 1000 s, non?repetitive at maximum i ppm and v cm , see electrical characteristics. 2. 1 square copper pad, fr?4 board 3. fr?4 board, using on semiconductor minimum recommended footprint, as shown in 403a case outline dimensions spec. electrical characteristics (t a = 25 c unless otherwise noted, v f = 3.5 v max. @ i f (note 4) = 30 a) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current i f forward current v f forward voltage @ i f 4. 1/2 sine wave (or equivalent square wave), pw = 8.3 ms, non?repetitive duty cycle. uni?directional tvs i pp i f v i i r i t v rwm v c v br v f electrical characteristics (t j = 25 c unless otherwise noted) parameter conditions symbol min typ max unit zener voltage (note 5) it = 1 ma v z 13.2 13.75 14.3 v reverse leakage current v rwm = 12 v i r 5.0 a clamping voltage i pp = 17.5 a (per figures 1 & 2) v c 15.6 v absolute maximum clamping voltage i ppm = 30.2 a (per figure 3, note 6) v cm 19.9 v 5. vz measured at pulse test it at an ambient temperature of 25 c. 6. absolute maximum peak current, i ppm .
SMBJ12AON http://onsemi.com 3 typical protection circuit v in v l z in load figure 1. 1.6 6.5 s pulse waveform figure 2. 8 20 s pulse waveform 01234 0 50 100 t, time (ms) value (%) half value ? i pp 2 peak value ? i pp t r 10 s figure 3. 10 1000 s pulse waveform figure 4. pulse derating curve peak pulse derating in % of peak power or current @ t a = 25 c 100 80 60 40 20 0 0 25 50 75 100 125 150 t a , ambient temperature ( c) 120 140 160 t p pulse width (t p ) is defined as that point where the peak current decays to 50% of i pp . 100 90 80 70 60 50 40 30 20 10 0 0 6.5 % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 1.6 s peak value i rsm @ 1.6 s half value i rsm /2 @ 6.5 s t, time ( s) 100 90 80 70 60 50 40 30 20 10 0 0204060 % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 8 s peak value i rsm @ 8 s half value i rsm /2 @ 20 s t, time ( s) 80
SMBJ12AON http://onsemi.com 4 application notes response time in most applications, the transient suppressor device is placed in parallel with the equipment or component to be protected. in this situation, there is a time delay associated with the capacitance of the device and an overshoot condition associated with the inductance of the device and the inductance of the connection method. the capacitive effect is of minor importance in the parallel protection scheme because it only produces a time delay in the transition from the operating voltage to the clamp voltage as shown in figure 5. the inductive effects in the device are due to actual turn-on time (time required for the device to go from zero current to full current) and lead inductance. this inductive effect produces an overshoot in the voltage across the equipment or component being protected as shown in figure 6. minimizing this overshoot is very important in the application, since the main purpose for adding a transient suppressor is to clamp voltage spikes. the smb series have a very good response time, typically < 1 ns and negligible inductance. however, external inductive effects could produce unacceptable overshoot. proper circuit layout, minimum lead lengths and placing the suppressor device as close as possible to the equipment or components to be protected will minimize this overshoot. some input impedance represented by z in is essential to prevent overstress of the protection device. this impedance should be as high as possible, without restricting the circuit operation. duty cycle derating if the duty cycle increases, the peak power must be reduced as indicated by the curves of figure 7. average power must be derated as the lead or ambient temperature rises above 25 c. the average power derating curve normally given on data sheets may be normalized and used for this purpose. v l v v in v in (transient) v l t d v v in (transient) overshoot due to inductive effects t d = time delay due to capacitive effect t t figure 5. figure 6. figure 7. typical derating factor for duty cycle derating factor 1 ms 10 s 1 0.7 0.5 0.3 0.05 0.1 0.2 0.01 0.02 0.03 0.07 100 s 0.1 0.2 0.5 2 5 10 50 1 20 100 d, duty cycle (%) pulse width 10 ms
SMBJ12AON http://onsemi.com 5 ul recognition the entire series has underwriters laboratory recognition for the classification of protectors (qvgv2) under the ul standard for safety 497b and file #116110. many competitors only have one or two devices recognized or have recognition in a non-protective category. some competitors have no recognition at all. with the ul497b recognition, our parts successfully passed several tests including strike voltage breakdown test, endurance conditioning, temperature test, dielectric voltage-withstand test, discharge test and several more. whereas, some competitors have only passed a flammability test for the package material, we have been recognized for much more to be included in their protector category.
SMBJ12AON http://onsemi.com 6 package dimensions smb do?214aa case 403a?03 issue d a s d b j p k c h notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. d dimension shall be measured within dimension p. dim min max min max millimeters inches a 0.160 0.180 4.06 4.57 b 0.130 0.150 3.30 3.81 c 0.075 0.095 1.90 2.41 d 0.077 0.083 1.96 2.11 h 0.0020 0.0060 0.051 0.152 j 0.006 0.012 0.15 0.30 k 0.030 0.050 0.76 1.27 p 0.020 ref 0.51 ref s 0.205 0.220 5.21 5.59 mm inches 0.085 2.159 0.108 2.743 0.089 2.261 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 SMBJ12AON/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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